The present invention relates to an output buffer circuit for transmitting a logic signal to a transmission line, and more particularly to an output buffer circuit that has a function of applying preemphasis to a transmission-output waveform so as to compensate signal attenuation in a transmission line.
The operating speeds of electronic circuit devices have been raised year after year, and research and development for realizing a higher-speed electronic circuit device have actively been performed. The realization of speedup of an electronic circuit device provides convenience in which, for example, processing that conventionally takes an extremely long time can be dealt with in a short time, or processing that has been thought to be impossible becomes possible. The speedup of an electronic circuit device reduces processing costs and contributes to enhancement of services in the world. In addition, the industry is further revitalized so as to manufacture the foregoing superior devices.
Because of realization of speedup of an electronic circuit device, the request for raising the speed of data-signal transmission, e.g., between LSI internal circuits that are constituent elements of an electronic circuit device, between LSIs, between printed wire boards, and between apparatus cases, has been enhanced.
As one of the techniques for raising the speed of data transmission, e.g., a technique, as disclosed in Japanese Patent Laid-Open Publication No. 2003-30946 (Patent Document 1), is known in which a termination resistor that matches the characteristic impedance of a transmission line is arranged at a signal reception unit so as to prevent the reflection of a received signal, thereby preventing data from being transmogrified by a reflected wave.
Moreover, in order to compensate the signal attenuation in a transmission line exemplified by an LSI inner wiring conductive strip, an LSI package wire, a printed-wire-board conductive strip, a cable, a connecter, and the like, an output buffer circuit, which has a preemphasis function for enhancing the signal amplitudes of high-frequency components in a signal or reducing the signal amplitudes of low-frequency components, has been put to practical use.
FIG. 7 is a configuration example of a conventional output buffer circuit disclosed in Patent Document 1. The foregoing output buffer circuit has an inverter 1, a delay circuit, a buffer, and a tri-state buffer, receives a data signal as an input, and outputs a transmission signal from an output terminal to a transmission line. The transmission line is connected at a reception terminal to a termination voltage Vt via a termination resistor Rt; the termination resistor Rt is made equal to the characteristic impedance of the transmission line so that no reflection wave is caused due to an impedance mismatch.
The inverter 1 receives a data signal and outputs an inverted signal. The delay circuit receives a data signal and outputs a delayed signal that is delayed by the duration corresponding to one cycle of the data. The buffer receives the inverted signal and outputs at the output terminal a transmission signal.
In the buffer, a P-type transistor 101 and an N-type transistor 102 operate complementarily to each other; the P-type transistor 101 and the N-type transistor 102 each have the same ON resistance Ra. The tri-state buffer receives the inverted signal and the delayed signal of a data signal and outputs at the output terminal a transmission signal. In the tri-state buffer, a P-type transistor 103 and an N-type transistor 106 each receive as an input the delayed signal of a data signal and operate complementarily to each other; the P-type transistor 104 and the N-type transistor 105 each receive as an input the inverted signal of the data signal and operate complementarily to each other. Accordingly, the configuration is in such a way that, in the case where an inverted signal and a delayed signal each have the same logical value, the tri-state buffer outputs an inverted logical value, and in the case where the inverted signal and the delayed signal do not have the same logical value, the tri-state buffer becomes OFF-state and does not drive the output terminal. The combined series on resistance of the P-type transistor 103 and the P-type transistor 104 and the combined series resistance of the N-type transistor 105 and the N-type transistor 106 each have the same ON resistance Rb.
FIG. 8 is a time chart for explaining the operation of a conventional output buffer circuit disclosed in Patent Document 1. At the time instant T1, a data signal transits from a low level to a high level; the inverted signal transits to the low level; the delayed signal remains at the low level. The P-type transistor 101 of the buffer and the P-type transistors 103 and 104 of the tri-state buffer each turn ON and the other transistors remain OFF-state. On this occasion, the output voltage of a transmission signal is Voh1. At the time instants T7 and T9, the situation is the same as that described above.
At the time instant T2, the data signal remains at the high level; the inverted signal remains at the low level; the delayed signal transits from the low level to the high level. The P-type transistor 101 of the buffer and the P-type transistor 104 and the N-type transistor 106 of the tri-state buffer each turn ON and the other transistors remain OFF-state. The tri-state buffer turns OFF, and the output voltage of the transmission signal is Voh2. At the time instants T3 and T10, the situation is the same as that described above.
At the time instant T4, the data signal transits from the high level to the low level; the inverted signal transits from the low level to the high level the delayed signal remains at the high level. The N-type transistor 102 of the buffer and the N-type transistors 105 and 106 of the tri-state buffer each turn ON and the other transistors remain OFF-state. On this occasion, the output voltage of the transmission signal is Vol1. At the time instants T8 and T11, the situation is the same as that described above.
At the time instant T5, the data signal remains at the low level; the inverted signal remains at the high level; the delayed signal transits from the high level to the low level. The N-type transistor 102 of the buffer and the N-type transistor 103 and the P-type transistor 104 of the tri-state buffer each turn ON and the other transistors remain OFF-state. The tri-state buffer turns OFF, and the output voltage of the transmission signal is Vol2. At the time instants T6 and T12, the situation is the same as that described above.
As described above, in the example of a conventional output buffer circuit, the output voltage of the transmission signal at the output terminal becomes Voh1 or Vol1 only for each one cycle during which the data signal changes, and becomes Voh2 or Vol2 at the other time instances; therefore, a preemphasis function is realized which enhances the signal amplitudes of high-frequency components in a signal or reduces the signal amplitudes of low-frequency components so as to compensate the signal attenuation in a transmission line.